1. Field of the Invention
This invention relates to access methods for computer memories, and more particularly, to a sequential memory access method and circuit which utilizes a single data pointer for control of the access to various memory units including, for example, a RAM unit and a ROM unit.
2. Description of Related Art
In memory devices with limited address/port provisions, the access methods are usually based on sequential memory schemes so as to save precious area on the circuit board. This will allow the computer system developer to have a large system space to put various components therein. Such sequential memory schemes include, for example, the PnP (Plug and Play) bus protocol specified by ISA (Industrial Standard Association). For efficient utilization of the limited area on the circuit board, the sequential memory circuit includes a RAM unit for storing volatile data, and a ROM unit for storing permanent data that are repeatedly used by the system. Such a conventional sequential memory system is composed of the following components:
(1) At least one RAM unit and one ROM unit, in which the RAM unit is used to store volatile data and the ROM unit is used to store permanent data.
(2) At least two data pointers, which are respectively used to address the RAM unit and the ROM unit. The value of each of the two data pointers will be increased by one after each access to the respective memory unit is completed.
(3) One length register, which is to record the length of the data to be written to or read from the RAM unit, and is also used to control the variation in the length of data stored in the RAM unit.
(4) One comparator, which is used to compare the contents of the length register and the RAM data pointer to determine whether the current access operation is being directed to the RAM unit or to the ROM unit. For example, when the RAM data pointer is greater in value than the length register, the current access operation is being directed to the ROM unit; otherwise the RAM unit is being accessed.
The foregoing system, however, has several drawbacks. First, the RAM unit and the ROM unit cannot be accessed at the same time, but two data pointers are used. Second, the use of two data pointers causes the system to be complex and less efficient. Third, there is a delay time in the comparator which causes a reduction to the overall system performance. The foregoing system will be described in more detail in the following with reference to FIG. 1.
Referring to FIG. 1, there is shown a schematic circuit diagram of a conventional sequential memory access circuit which allows an external system 10 to perform an access (Read/Write) operation on various memory units including, for example, a RAM unit 13 and a ROM unit 14. This sequential memory access circuit includes a RAM data pointer circuit (Y) 11, a ROM data pointer circuit 12, a comparator (X-Y) 15, a length register (X) 16, a Write.sub.-- Data bus which is used to transfer data from the external system 10 to the RAM unit 13 and the length register (X) 16, and a Read.sub.-- Data bus which is used to transfer data from the RAM unit 13 and the ROM unit 14 to the external system 10. The external system 10 issues three control signals including RESET (reset signal), Read (read request signal), and Write (write request signal) to the RAM data pointer circuit 11 for control of the access operation to the RAM unit 13 and the ROM unit 14.
At first, the external system 10 issues the RESET signal to set the pointer value in the RAM data pointer circuit 11 and the ROM data pointer circuit 12 to zero so as to initiate a sequential access operation to the RAM unit 13 or the ROM unit 14. When the external system 10 reads data from the RAM unit 13 and ROM unit 14, for example, it sets Read at a LOW voltage, and the accessed data will be put on the Read.sub.-- Data bus for the external system 10 to fetch data from the same. On the other hand, when the external system 10 wants to write data into the RAM unit 13, it sets Write at a LOW voltage and puts the data on the Write.sub.-- Data bus, which causes the data on the Write.sub.-- Data bus to be written into selected areas of the RAM unit 13. At the same time, the content X of the length register 16 and the current pointer value Y of the RAM data pointer circuit 11 are forwarded to the comparator 15 which compares the two inputs X, Y to thereby generate an output in accordance with the following criteria:
(A) If X&gt;Y, the output of the comparator 15 will update the pointer value of the RAM data pointer circuit 11 in accordance with the states of Read and Write. PA1 (B) If X.ltoreq.Y, the output of the comparator 15 update the pointer value of the ROM data pointer circuit 12 in accordance with the state of Read. At this time, the RAM data pointer circuit 11 is disabled.
At this time, the ROM data pointer circuit 12 is disabled, while the access operation to the RAM unit 13 is enabled.
One major drawback of the foregoing sequential memory access circuit, however, is that the RAM data pointer circuit 11 and the ROM data pointer circuit 12 cannot operate at the same time. This causes the use of extra hardware that significantly increases the manufacturing costs of the sequential memory access circuit. Moreover, since the comparator 15 is built with adders and subtractors, it requires a large circuit layout area to implement, and the data processing rate is low due to a delay time inherent to such a construction.